1. Field of the Invention
The present invention relates to semiconductor chips, and more particularly, to the formation of capacitors within a semiconductor device.
2. Description of the Related Art
In today's high powered computing world, many processors' frequencies are in the gigahertz (GHz) range. Consequently, capacitors are often required to shunt high frequency and high current AC components that are inevitably coupled onto system power buslines. These capacitors, typically named de-coupling capacitors, are integrated either on-die (adds wafer cost) or on-package (adds package cost). Therefore, large costs may be associated with the usage of capacitors when using either of the above methods.
Capacitors can be utilized in a cost effective manner when used at the wafer level. Unfortunately, this method also has other problems. The common approach to capacitor usage on the wafer level is to build the de-coupling capacitor at lower metal levels such as, for example, M1–M3. This involves using at least 2 layers of metal and therefore requires a via to make the connection from a top metal line to a top capacitor plate located over the dielectric of the capacitor and the bottom capacitor plate. This kind of approach is useful if a small amount of capacitance is needed. Unfortunately, when large amounts of capacitance are desired, this approach becomes problematical because the aforementioned capacitor structures do not have large capacitance plates due to limited space in the lower levels of the semiconductor structure. In addition, the prior art method requires usage of dedicated space within the semiconductor structure taking away valuable space that could be used for other semiconductor structures.
FIG. 1 shows a typical prior art semiconductor structure 10. The semiconductor structure 10 includes a metal line 12 connected to a top capacitor plate 14 and connected to metal lines 22 and 20 at a lower metallization level by use of vias 16 and 18 respectively. In one typical example, the via 16 from the metal line 12 is connected to the top capacitor plate 14. The top capacitor plate 14 is separated from the metal line 22 by a dielectric layer 15. Unfortunately, the structure 10 defined by the top capacitor plate 14, the dielectric layer 15 and the metal line 16 can only produce a small amount of capacitance and in addition takes up dedicated space within the semiconductor device.
In view of the foregoing, there is a need for capacitors that do not occupy dedicated space within the semiconductor device and can generate larger amounts of capacitance than the prior art structures.